Semiconductor devices continue to be scaled to smaller and smaller dimensions. One of the problems caused by shrinking dimensions is field isolation thinning an small dimensional regions. More specifically, when the space between nitride features becomes less than two macrons the thickness of the field oxide grown an this small region can differ greatly from nitride grown in a large region. More specifically, for a spacing between nitride features of 2 macrons, a field oxide thickness of about 7500 angstroms would be achieved. However, for a spacing of 0.9 microns between nitride features, the same field oxide process would produce field oxide having a thickness of about 5900 angstroms. The locally thinner field isolation region combined with oxide removals can greatly decrease the thickness of the field of isolation region to less than half of what was originally grown. Using the previous example, only about 3000 angstroms of the original 5900 angstroms remains when a high potential electrode is formed on the field oxide.
A problem associated with this thinner field oxide is the creation of a field device that has an unacceptably low threshold voltage. This is particularly problematic when a gate electrode over the field isolation region is at a relatively high potential (higher than V.sub.DD). When the gate electrode is at the relatively high potential, current can flow between the source/drain regions under the field isolation region, which is undesired.
Therefore, a need exists for forming a semiconductor device having reasonably high field threshold voltages. A need also exists that such a semiconductor device be formed without adding any processing steps or masking layers, so that processing time and costs are minimized.